Staff/Principal Verification Engineer (OVM/UVM in Lake Forest, CA

Staff or Principal Verification Engineer - High Speed SoCs Staff or Principal Verification Engineer - Growing IPO Bound IC Startup - OVM - UVM - Skills Required - Design Verification, SystemVerilog, OVM, UVM, VMM, SystemC, C++, SONET, OTN, Ethernet
Headquartered in Orange County, CA, we are a Well-Funded, VC-Backed, Award Winning, and Exciting Pre-IPO startup that has seen tremendous growth. Because of our recent successes with our custom high-speed SoCs, we are currently ramping up and looking to add a Staff or Principal Verification Engineer to develop leading edge verification methodologies.
The Verification Engineer should have strong hands-on experience in SystemVerilog with OVM, UVM, or VMM methodologies.
What's in it for you